AMD’s Zen 6 EPYC Venice Pictured as a 256-Core Monster, Massive Twin I/O Dies & First 2nm HPC Chip To Enter Volume Ramp - Wccftech

What the report says

Wccftech reported that AMD displayed its next-generation EPYC “Venice” server processor during its Advancing AI 2026 event presence at Moscone Center West in San Francisco. The chip, based on AMD’s Zen 6 architecture, was shown on event signage spotted by Computerbase and described by Wccftech as a flagship 256-core part for the company’s 6th Gen EPYC lineup.

According to the report, the Venice design uses eight compute dies, each associated with 32 cores, alongside two large central I/O dies. Wccftech said the platform is expected to support features such as PCIe 6.0, UCIe and DDR5, and described the processor as AMD’s first high-performance computing product entering volume production on TSMC’s 2nm process. The article also cited AMD’s previously stated targets of more than 70% gains in performance and efficiency and more than 30% higher thread density for Venice.

The report places Venice within AMD’s broader push into AI infrastructure, particularly its Helios AI rack systems. Wccftech framed the CPU launch as important because emerging agentic AI and reinforcement-learning workloads may increase demand for high-core-count server processors alongside GPUs.

For context, AMD’s EPYC chips compete in the data center CPU market against offerings from Intel and, increasingly in AI rack systems, Nvidia’s Arm-based Vera CPUs. Wccftech said AMD has compared its current and upcoming EPYC processors favorably against Nvidia’s Vera platform, though those claims should be treated as vendor-provided performance positioning until independently tested.